Microelectronic devices are generally fabricated on the surface of slices or wafers of single-crystal (mono-crystalline) silicon. These wafers are sliced from long cylindrical ingots of single-crystal silicon (c-Si) known as boules, which take their cylindrical shape from the way the crystal is grown and drawn from a silicon melt. The wafers sliced from the boule are consequently thin discs of nearly perfectly ordered crystalline material and are cut so that the surface is parallel to one of the primary crystallographic planes. While it is generally straightforward to pull a longer boule from the melt, increasing the diameter of the boule while maintaining the quality of the crystal is a challenging technological feat. Nevertheless, over the decades of development of the microelectronics industry, wafer diameters have gradually increased, driven by improved crystal pulling technology and pressure to reduce costs by packing more chips on each substrate. Wafer sizes have evolved through the following widely used diameters: 24.5 mm, 50 mm, 76 mm, 100 mm, 125 mm, 150 mm, 200 mm, and currently 300 mm.
While modern microelectronic circuits such as microprocessors depend critically on the nearly perfect structure of the crystal lattice for their high speed transistors, other applications of silicon-based electronics such as flat panel displays and solar photovoltaics have emerged, which can tolerate a tradeoff: poorer material properties, such as lower charge carrier mobility, in favor of other desirable features such as lower cost, larger size, and optical transparency.
Flat Panel Displays
In the field of flat panel displays, such as LCDs for example, the electronic backplane that switches the pixels of the display has generally been built starting from a thin film of disordered amorphous silicon (a-Si) deposited onto a glass substrate. The performance of an a-Si transistor is quite poor compared to that of c-Si, however, it is possible to deposit a-Si over large areas of low-cost glass economically, and the thin film of a-Si can be transparent to light, making the a-Si transistor acceptable in many flat panel display applications.
Intermediate in performance between a-Si transistors and c-Si transistors are transistors fabricated from poly-silicon (p-Si), a material which is a agglomeration of tiny crystalline grains each having crystalline order internally, but being oriented randomly with respect to each other.
Demand for displays that are thinner, lighter, faster, and brighter has led to the development of higher performance p-Si transistors fabricated on low-cost glass substrates. Polysilicon deposition, however, normally requires process temperatures that are higher than the softening temperature of display glass. This limitation was overcome by using an excimer laser beam scanned over an a-Si film thereby recrystallizing a-Si into p-Si. The laser's energy is deposited mainly into the thin film on the surface, with minimal heating of the underlying glass. While this approach has had some success in the marketplace, the recrystallization process is difficult and expensive and still does not produce transistors with the performance of c-Si.
Solar Photovoltaics
A similar set of tradeoffs exist in the solar photovoltaic field. Solar cells fabricated from sliced c-Si or p-Si boules have the higher efficiencies for converting sunlight into electrical energy but they have the attendant difficulties of slicing up the boule, the wasted material associated with the sawing process, and the expensive handling, tiling and connecting of large numbers of slices together into solar arrays. For example, four sides of a cylindrical silicon boule are generally sawn off. This is so that when the slices are tiled together in an array, they fit together well and capture most of the sunlight striking the solar panel. However this trimming often does not completely cut the circular boule down to square cross-section, but rather leaves a square with rounded corners in order to reduce the quantity of trimmed material. The resulting corner area where four slices in an array meet does not collect sunlight, resulting in reduced efficiency.
On the other hand, monolithic solar cells may also be fabricated by depositing a-Si on large sheets of low-cost glass with little material waste, but their inherent light-to-electricity conversion efficiency is relatively low as a result of the poorer properties of the a-Si material.
Ion-Cut Process
Another semiconductor manufacturing process that is widely known is the ion-cut process. This process involves directing an ion beam, generally hydrogen or helium ions, at a crystalline substrate such as a silicon wafer and implanting the ions beneath the surface. The ions come to rest in a thin layer below the surface, the depth of which is dependent on the initial mass and energy of the ions. The depth can be reliably predicted using well-known theories of charged particle interactions with matter. The widely used TRIM or SRIM software code is often used to perform these calculations. FIG. 2 shows data from SRIM relating the penetration depth (known as ‘projected range’) of hydrogen ions into silicon as a function of incident ion energy. For example, hydrogen ions impinging on silicon at 3 MeV will stop at a depth of approximately 92 micrometers below the surface, in the range of typical thickness for crystalline solar cell fabrication. In general, ion-cut process energies can range from tens of keV for very thin bonded layers, up to arbitrarily high energies for thick, self-supporting slices.
The resulting subsurface damage layer is concentrated around the depth where the ions stop and it weakens the crystal structure at that depth. Subsequent heating of the substrate may also serve to consolidate the implanted gas and nucleate and grow micro-bubbles, further weakening the crystal lattice. Given a sufficient dose of implanted ions and the appropriate application of heat or other source of stress to initiate cleavage, the crystal can be induced to cleave along the plane of the implanted layer. The prior art has involved the formation of damage layer coincident with a single crystal plane, hence the appropriateness of the word ‘cleave’
By bonding a so-called ‘handle’ substrate to the top surface of the implanted ‘donor’ substrate prior to the cleavage step, it is possible to produce a wide variety of novel composite materials composed of a film of donor material attached to a thicker substrate of handle material. The use of this process to combine otherwise incompatible materials into novel composites is widely known in the art, as are a variety of bonding techniques. The most important application of this process has been to silicon-on-insulator materials which have found wide commercial acceptance.
The potential for the use of the ion-cut process in solar cell manufacture is described in the technical literature, for example: “Crystalline thin-film silicon solar cells from layer-transfer processes: a review”, R. Brendel, Proc. 10th Workshop on Crystalline Silicon Solar Cell Materials and Processes, Aug. 13-16, 2000, Copper Mountain, USA, B. L. Sopori,ed. Thin films which are bonded to a thicker substrate such as glass for mechanical support are possible, as are thicker slices which are mechanically self-supporting. The advantage of ion-cut over conventional c-Si or p-Si slices cut from billets by wire-saw, is that the slices can be cut as thin as desired with minimal wasted material due to the thickness of the cutting tool (kerf loss). Nevertheless, the cost and complexity of handling and assembly of numerous slices still exists, as does the efficiency loss due to corner radii.
Similarly, in the field of flat panel display manufacture, U.S. Pat. No. 6,818,529 by Bachrach et al. proposed using the ion-cut process to produce large area film of c-Si by tiling a plurality of thin c-Si polygons across a glass sheet. The boule from which the silicon is sliced is pre-cut to a polygonal cross section to allow the slices to fit neatly together, and the bonding step occurs prior to the cleaving so that the silicon film is always supported. The inevitable gaps between tiles are said to be filled with deposited silicon, annealed and planarized. The degree of commercial success of this process is not known to the present applicant, however the difficulty and cost of manufacture is apparent: aligning, bonding and cleaving multiple separate billets as well as inhomogeneities in film properties between the tiles.
It is evident from these examples, although not limited to them, that it would be highly useful and advantageous to have a means for producing large continuous areas of mono-crystalline silicon films.